Qualcomm Design Flow Development- Staff Engineer - Qualcomm - Cork, Ireland in Cork, Ireland
Job Id E1960538
Job Title Design Flow Development- Staff Engineer - Qualcomm - Cork, Ireland
Post Date 02/22/2018
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location Ireland - Cork
Job Overview Qualcomm Technologies Inc (QTI) is the world leader in wireless ICs powering the majority of 4G & next generation devices, is the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortunes list of 100 Best Companies to Work For. Qualcomms Design Flow Development team defines and enables the RTL to GDSII implementation flows for variety of advanced low power and high performance SOCs, enabling state-of-the-art mobile chipsets from Qualcomm.
The Design Flow Development team is looking for outstanding engineers with experience in Physical Design for High performance and/or lower power cores and aptitude for debug design issues and enable seamless quality of tools and flows. The candidate will drive best-in-class RTL to GDSII flows qualification for >1billion device SOCs in 10nm and smaller FinFET technologies. If you have expertise in these areas and are excited by driving leading edge semiconductor technologies to real life, this is the opportunity for you.
The engineer will be responsible for quality and verification for advanced implementation technologies and flows for Synthesis, Place and Route and sign-off for Mega SoCs with unique challenges driven by Low power architecture of Qualcomm designs.
-Enable rollout of robust design flows, identify areas for flow improvement, coordinate implementations of improvements.
-Develop and qualify flows optimized for Area, performance and power QoR
-Provide tool support and issue debugging services to design teams.
-- Participating in project proposal development including key milestones and deliverables
Execute and deliver project goals in a timely manner
Resolve issues in all phases of development to assure smooth project execution
Conduct regular project technical review with internal and external collaborating teams on specific projects driven by the timing team
Minimum Qualifications -Experience in leading HM / full-chip synthesis, Constraints, Timing closure & Physical Design activities.
Proficient in Synopsys, Cadence SOC implementation and sign-off flows.
strong CAD automation using: Python, Tcl/Tk, PERL, HTML, C++.
Proficient in UNIX
Preferred Qualifications Additional expertise in one or more of the following areas:
STA tool and timing closure methodologies
Developing and implementing timing ECOs including affect on congestion/routing/power
Power grid, clock tree, and low-power reduction implementation methods
Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing
Floorplanning, Placement, CTS, P&R
Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
Circuit level comprehension of time critical paths in the design
Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM)
2+ year industrial experience preferred.
Work independently and with multisite teams in the areas of RTL to GDSII implementation
-Good communication skill and personal skills in a multi-disciplinary, fast pace engineering environment
- Will consider all levels of seniority assuming relevant academic experience.
Education Requirements Preferred: Master's, Computer/Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.