Qualcomm Digital ASIC Design Engineer(s) (PPA) All levels - QCT, Cork, Ireland in Cork, Ireland

Job Description:

Job Id E1959622

Job Title Digital ASIC Design Engineer(s) (PPA) All levels - QCT, Cork, Ireland

Post Date 03/21/2018

Company-Division Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location Ireland - Cork

Job Overview Qualcomm CDMA Technologies, a.k.a. QCT http://www.qualcomm.com/qct/, is the industry leader in 3G, 4G and 5G communication technology, the largest fabless semiconductor company in the world and is consistently ranked among Fortunes 100 Best Companies to Work For.

QCT offers solutions for CDMA, UMTS, GSM and LTE technologies, providing support for both 3G, 4G and 5G networks and devices. Qualcomm also offers a broad portfolio of additional wired and wireless technologies for the mobile, networking, computing and consumer electronics product segments. Our combined portfolio now features an expanded array of high-performance, end-to-end solutions ranging from Wi-Fi, GPS, Bluetooth, FM and Ethernet to HomePlug Powerline and passive optical network (PON) technologies.

All of our solutions and products are elegantly engineered for optimal performance and power consumption. And our system-on-chip solutions like Snapdragon bring together CPU, GPU, connectivity, multimedia and GPS technologies in a way that is redefining mobile possibilities for people everywhere. Because of its unsurpassed performance and capabilities, Snapdragon is enhancing the mobile experience and fueling an ever-expanding array of new connected device categories, ranging from smartphones to tablets to e-readers and beyond.

QCTs Digital ASIC Team is actively seeking candidates for Technology PPA and 3rd-Party IP enablement

positions at our Cork, Ireland location. You will be part of the design team that will drive and execute on all phases of the ASIC design flow for MSM and MDMs at the core and chip-level using advance process nodes, including 10nm (in production) and 7nm CMOS technology.

Minimum Qualifications -Technical Leadership

-Performance, Power and Area Analysis

-Low Power Design

-Scripting with Shell, Tcl, Perl or Python

-RTL Synthesis with Synopsys DC

-Netlist to GDS

-Floorplanning with Cadence Encounter or similar tools

-Auto Place and Route with Cadence Innovus or Synopsys ICC2 or similar tools

-Parasitic Extraction with Synopsys StarRC or similar tools

-Static Timing Analysis with Synopsys Primetime or similar tools

-Signal Integrity Analysis with Synopsys PTSI or similar tools

-ECO generation using Synopsys Primetime or Dorado Tweaker or similar tools

-Physical Verification DRC/LVS/ERC using Mentor Calibre or similar tools

-Logic Verification using Cadence LEC or similar tools

-Power-Grid Voltage Drop Analysis using Apache Redhawk

Preferred Qualifications Role & Responsibilities

As a Design Engineer, you will play a vital role in addressing challenges with Performance, Power, and Area (PPA) scaling tradeoffs to qualify technology entitlement of advance process nodes. You will be responsible for convergence of complex designs using best-in-class tools, flows & methodologies to optimize PPA. You will also benchmark 3rd-party IP designs, analyze performance and quality metrics, publish tradeoffs for IP recommendations, drive enablement and schedule for IP integration into Qualcomms SoC and IoT products, track development through tapeout, achieve 100% yield target post-Silicon, and signoff IP designs for high-volume production.

Education Requirements Required: Bachelors in Engineering

Preferred: Masters Degree in Engineering a plus

Preferred: 5+ years of technical experience a plus

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.